1. Field of Invention
The present invention generally relates to semiconductor devices equipped with a test mode and a method for operating the same. More particularly, the present invention relates to a semiconductor device with a built-in measurement circuit that supports examinations of the semiconductor device when the semiconductor device is examined by a test apparatus such as an IC tester in a test mode.
2. Description of Related Art
FIG. 3 shows a conventional semiconductor device. In the semiconductor device shown in FIG. 3, buffer circuits 101, 102, 103, . . . , each having two inverters, are inserted as input circuits between input terminals 1, 2, 3,. . . and an internal circuit 30.
As shown in FIG. 3, when input data is applied to the input terminals 1, 2, 3, . . . from a test apparatus such as an IC tester, the input data is supplied to the internal circuit 30 through the buffer circuits 101, 102, 103, . . . , respectively. Therefore, when this type of semiconductor device is examined by using the test apparatus, logic levels to be inputted in the internal circuit need to be measured. For this purpose, it is proposed to provide a measurement circuit that operates in a test mode within the semiconductor device, to thereby measure logic levels that are inputted in the internal circuit. In the semiconductor device shown in FIG. 3, for example, AND circuits 21, 22, 23, . . . , each including a NAND gate and an inverter, are provided as measurement circuits.
The AND circuits are connected to a series of the data input terminals in a chain like manner. More particularly, for example, input data from the second data input terminal 2 is supplied through the buffer circuit 102 to one of two inputs of the second AND circuit 22. Also, an output from the AND circuit 21 that is connected to the second AND circuit 22 in an immediately proceeding stage is supplied to the other input of the AND circuit 22. Furthermore, an output of the AND circuit 22 is supplied to one input of the AND circuit 23, and input data from the third data input terminal 3 is inputted to the other input of the AND circuit 23. In this manner, the multiple AND circuits are connected in a chain-like manner.
A test mode signal TEST is supplied through a test mode signal input terminal 60 to one input of the AND circuit 21 in the first stage. The test mode signal TEST is at high level in a test mode. Also, an output of one of the AND circuits in the last stage is supplied to one input of a selection circuit 70. An output of the internal circuit 30 is supplied to the other input of the selection circuit 70. The selection circuit 70 is controlled by the test mode signal TEST. The selection circuit 70 selects the output of the internal circuit 30 in a normal operation mode, and selects the output of the AND circuit in the last stage in a test mode. An output of the selection circuit 70 is read out through an output terminal 80 by an external device.
It is noted that, in the normal operation mode, the test mode signal TEST is at low level. Therefore, outputs from the AND circuits 21, 22, 23, . . . are at low level without regard to the level of the input data. On the other hand, the test mode signal TEST is at high level in the test mode. Therefore, when input data on input systems other than an input system that is subject to measurement are fixed at high level, and the logic level of input data (for example, input data applied to the data input terminal 1) in the input system that is subject to measurement is changed, the logic level inputted in the input system of the internal circuit 30 is accordingly changed. The change is transferred through the AND circuits 21, 22, 23, . . . that are connected in a chain-like manner, and outputted through the selection circuit 70 and then through the output terminal 80. In this manner, the logic level of an input within the internal circuit 30 can be measured without regard to differences in the specification of the input circuits of the semiconductor device.
When the buffer circuits are used as input circuits in a manner shown in FIG. 3, a problem occurs when a power supply to a separate system that supplies input data is tuned off. In other words, in such an instance, the data input terminals of the semiconductor device are placed in a high-impedance state, an input to the buffer circuits may have a potential close to an intermediate potential between a power supply potential VDD and a power supply voltage VSS, i.e., a value of (VDD+VSS)/2. Alternatively, an input to the buffer circuits may have a potential close to a value of VDD/2 when a power supply voltage VSS is at a grounding potential. As a result, a drain current may constantly flow through the inverters that form the buffer circuits.
In order to prevent wasteful current from flowing even in the instance described above, some techniques are proposed. For example, an AND circuit 11 shown in FIG. 4 or an OR circuit 91 shown in FIG. 5 is used to form an input circuit instead of the buffer circuit 101 used in the semiconductor device shown in FIG. 3.
Referring to FIG. 4, the AND circuit 11 includes a NAND gate and an inverter. One of input terminals of the NAND gate is connected to the data input terminal 1. The other input terminal of the NAND gate is supplied with a control signal C that is internally generated in the semiconductor device. Even when the data input terminal 1 is placed in a high-impedance state, an output of the NAND gate of the AND circuit 11 is always at high level if the control signal C is maintained at low level. Therefore, wasteful current does not flow.
Referring to FIG. 5, the OR circuit 91 includes a NOR gate and an inverter. One of input terminals of the NOR gate is connected to the data input terminal 1. The other input terminal of the NOR gate is supplied with a control signal C bar that is internally generated in the semiconductor device. Even when the data input terminal 1 is placed in a high-impedance state, an output of the NOR gate of the OR circuit 91 is always at low level if the control signal C bar is maintained at high level. Therefore, wasteful current does not flow.
However, when the semiconductor device having an input circuit that is formed with the AND circuit 11 shown in FIG. 4 is tested, the output of the AND circuit 11 is fixed at low level and does not change even when the logic level on the data input terminal 1 is changed, unless the control signal C is changed to high level. Also, when the semiconductor device having an input circuit that is formed with the OR circuit 91 shown in FIG. 5 is tested, the output of the OR circuit 91 is fixed at high level and does not change even when the logic level on the data input terminal 1 is changed, unless the control signal C bar is changed to low level.
Accordingly, when the AND circuit 11 shown in FIG. 4 or the OR circuit 91 shown in FIG. 5 is inserted in an input system of the semiconductor device having a measurement circuit that uses the AND circuits 21, 22, 23, . . . shown in FIG. 3, the logic level of an input in the input circuit cannot be measured unless the internal control signal is changed.
In view of the above, it would be desired to provide a semiconductor device having an input circuit and a method for operating the same, in which the logic level of an input on the input circuit can be measured by a test apparatus such as an IC tester even when a gate circuit that uses an internally generated control signal is used in a first stage of the input circuit.
A semiconductor device in accordance with one exemplary embodiment of the present invention has an internal circuit in which input data is gated and supplied to the internal circuit according to an internal control signal generated within the semiconductor device. The semiconductor device has N number (N being two or greater integers) of data input terminals for inputting input data, and a test mode input terminal for inputting a test mode signal. An OR device is provided for obtaining a logical sum of the internal control signal and the test mode signal. The semiconductor device also has N number of gate circuits that are supplied with the input data applied to the N data input terminals, respectively. When an output of the OR device is active, those of the N gate circuits responsive to the output of the OR device pass the input data applied to the data input terminals. The internal circuit is supplied with outputs of the N gate circuits. The semiconductor device has a first stage AND device and second through Nth stage AND devices. The first stage AND device has a first input that is supplied with an output of a first one of the N gate circuits and a second input that is supplied with the test mode signal. The second through Nth stage AND devices respectively have first input terminals that are supplied with outputs of second through Nth ones of the N gate circuits, respectively, 25 and second input terminals that are supplied with outputs of the first through (Nxe2x88x921)th stage AND devices, respectively.
The semiconductor device may further include a selection circuit that selects an output of the internal circuit in a normal operation mode and selects an output of the Nth stage AND device in a test mode, and an output terminal that is supplied with an output of the selection circuit.
In the semiconductor device, the internal control signal and an output of the OR device may be active at high level. Alternatively, the internal control signal and an output of the OR device may be active at low level.
By a semiconductor device having the structure described above in accordance with the embodiment of the present invention, even when a gate circuit that uses an internally generated control signal is used in one of the input circuits in the first stage thereof, the operation of the gate circuit can be controlled by using a test mode signal. Therefore, the logic level of an input in the input circuits can be measured by using a test apparatus such as an IC tester.
Other features and advantages of the invention will be apparent from the following detailed description, taken in conjunction with the accompanying drawings that illustrate, by way of example, various features of embodiments of the invention.